Photolithography is a process commonly used for defining features during semiconductor wafer processing, for example during the fabrication of integrated devices (and, in a specific case, integrated circuits or ICs), micro electro-mechanical systems (MEMS), or micro opto-electro-mechanical systems (MOEMS), collectively referred to herein as integrated devices. Photolithography generally involves applying a photoresist material (“resist”) to a wafer, irradiating the resist using chosen radiation (for example, light) the spatial distribution of which is appropriately patterned, then developing the patterned resist, etching a material of the wafer or depositing different materials on the parts of wafer exposed in the patterned resist, and, finally, removing the remaining resist after etching or deposition of the materials. In photolithography, a critical dimension (CD) is a characteristic size that corresponds to various features critical to the integrated device performance that need to be patterned on a chosen surface (such as the wafer surface, for example), e.g., a target feature width, length and/or spacing between features.
The process of integrated device fabrication involves multiple steps of resist patterning followed by wafer etching or materials deposition. During such fabrication process, patterns are laid down on a reticle, the image of which is later formed with a photolithography tool on a target substrate (such as a semiconductor wafer) in a sequence of patterning steps. The formation of an image of the reticle is followed by the process of formation (which may include the etch and/or deposition processes) of features the shapes of which correspond to the shapes laid down on the reticle. Each pattering step results in fabrication of a patterned layer of material that overlaps with some other layers fabricated at different steps of the integrated device fabrication process. As a result, integrated devices contain stacks of layers with overlapping geometrical patterns formed in various materials, and connected with the patterns in different layers of these integrated devices.
While the CD-control of lithographic patterns is an important aspect of the lithographic process used to ensure that the end product meets the design specification, related art overlooks the fact that performance of the integrated device components fabricated by lithographic exposure is determined not only by the shapes and CDs of the lithographic patterns, but also by mutual positioning of the edges of various image patterns—for example, by locations of the edges of a given image pattern in a given layer of the integrated device relative to (or with respect to) those of patterns in various other layers of the integrated device. Empirical evidence suggests that precise determination and monitoring of the locations of pattern edges proves to be critical for accurate and precise integrated device fabrication. Indeed, spatial misplacement of an image pattern (that, otherwise, has correct shape and dimensions) in a chosen layer of the integrated device relative to image patterns in integrated device layer(s) located above or below such chosen layer leads to degradation of operation of the integrated device or its malfunction. The yield of integrated device manufacture is determined not only by how well and/or precisely the individual layers of integrated devices are patterned, but also by how well patterns in various integrated device layers are aligned with respect to other patterns in other layers.
The time between the initial lithographic process development to manufacturing implementation of the developed process has shrunk dramatically in recent years. In general, it is rarely feasible to experimentally evaluate and optimize all aspects of a lithographic process prior to manufacturing introduction. It is well recognized that ability to predict and to monitor the pattern edges is critical to successful control of integrated device manufacture (see, for example, Progler, Bukofsky, and Wheeler, “Method to Budget and Optimize Total Device Overlay”, SPIE Vol 3679, pages 193-207, 1999). What is more critical, however, is the process of configuring the optical projection system used for the formation of an image on the target substrate such as to minimize the pattern overlay errors alluded to above. While the related art addresses the image overlay procedure and describes pattern edge placement with the use of the results of measurement of overlay marks, the related art does not explain how to measure the spatial errors of the pattern edge placement on a target substrate with respect to the ideal location(s) of such placement. The related art is also silent with respect to a projection optics system that would allow the image overlay to be minimized or otherwise corrected (let alone how to tune the existing projection system, used to create the very images participating in the image overlay) in order to minimize or correct the image overlay. Furthermore, while emphasizing the device overlay budget, the related art does not address co-optimization of the pattern imaging and placement by adjusting entire imaging setup, including illumination and aberration contents of the projection optics. The solutions to such co-optimization and modification of the used-for-patterning projection optical systems are required.